The present invention relates to the adjustment of transitions within a bit stream, in particular for adjustment of transitions within a bit stream on an output signal of an electronic device to be tested.
For testing electronic devices, in particular integrated electronic circuits providing digital electrical output signals, a test or stimulus signal is fed to an input of the device under test, in the following abbreviated as DUT, and a response signal of the DUT is evaluated by an automatic test equipment, in the following abbreviated as ATE, for example by comparison with expected data.
The output signals of modern integrated electronic circuits often exhibit non-deterministic clock latencies between activities even if they are stimulated with the same stimuli. During production test of those devices, prior art test equipment expects to do a bit level comparison against a fix pre-computed stream of expected bits. In the presence of non-deterministic behavior these tests will fail, even though the DUT is operating correctly.
The reasons for non-deterministic output timing are beyond others process variations causing unknown but static timing variations, temperature variations of the clock insertion delays causing unknown and time varying timing drift, initial random bits after reset or start-time latencies, on-chip or inter-chip signal cross clock-domains resulting in non-deterministic idle time, in particular with non-trivial fractional ratios, and jitter causing unknown and non-deterministic timing variations.